In a hierarchical design approach, the logic of an integrated circuit (“IC”) or chip is partitioned into smaller portions that are assigned to predefined areas of the chip. These smaller design portions (which may comprise area, logic, interconnects and timing assertions) are typically referred to as macros. Usually, some logic will not be assigned to any macro. This logic is considered as being on the top level of the hierarchy. It may well be that the hierarchy is nested and a chip is partitioned into one or more units and each unit is partitioned into one or more macros. The top level is typically referred to as a “unit” and the lower level(s) as “macros”.
A port of a macro is the point (or small area) at which the internal and external signals are connected to each other. There are some guidelines from the design team on which ports should be close to each other. The size of the macro as well as the x- and y-dimension of the macro outlines are given and assumed to be fixed. During unit/chip placement these fixed macro outlines are moved around to find the best legal location non-overlapping and with minimum netlength between ports. Additional unit/chip blockages allow not all possible placements and lead to longer netlength.